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Texas Instruments /MSP432P4011 /SYSCTL_A /SYS_SRAM_STAT

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Interpret as SYS_SRAM_STAT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BNKEN_RDY_0)BNKEN_RDY 0 (BLKRET_RDY_0)BLKRET_RDY

BNKEN_RDY=BNKEN_RDY_0, BLKRET_RDY=BLKRET_RDY_0

Description

SRAM Status Register

Fields

BNKEN_RDY

When 1, indicates SRAM is ready for access and banks can be enabled/disabled.

0 (BNKEN_RDY_0): SRAM is not ready for accesses. Banks are undergoing an enable or

disable sequence, and reads or writes to SRAM are stalled until the banks are

ready.

1 (BNKEN_RDY_1): SRAM is ready for accesses. All SRAM banks are enabled/disabled

according to values of registers SYS_SRAM_BANKEN_CTLx (x=0,1,2,3)
BLKRET_RDY

When 1, indicates SRAM is ready for access and blocks can be enabled/disabled for retention.

0 (BLKRET_RDY_0): SRAM blocks are being set up for retention. Entry into LPM3, LPM4 should

not be attempted until this bit is set to 1

1 (BLKRET_RDY_1): SRAM is ready for accesses. All SRAM blocks are enabled/disabled for

retention according to values of registers SYS_SRAM_BLKRET_CTLx

(x = 0,1,2,3)

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Register License

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Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data